`include "SimTop.v"
//~ `New testbench
`timescale  1ns / 1ps

module testbench (
    
    );

    reg clk = 0, rst = 1;

    reg [31:0] master_data = 0;
    reg master_en          = 0;
    wire master_busy          ;

    wire slave_en             ;
    wire [31:0] slave_data    ;
    reg slave_busy         = 0;

    parameter period = 10;

    initial begin
        clk = 0;
        forever #(period/2) clk = ~clk;
    end

    initial begin
        #period rst = 0;
    end

    SimTop SimTop_inst (
        .clk(clk),
        .rst(rst),
        
        .master_en  (master_en  ),
        .master_data(master_data),
        .master_busy(master_busy),


        .slave_en   (slave_en   ),
        .slave_data (slave_data ),
        .slave_busy (slave_busy )
    );

    integer i = 0 ;


    initial begin

        slave_busy = 0;
        for (i = 0;i<100; i=i+1 ) begin
            @(posedge clk) begin
                if(i%10 == 0) begin
                    if(master_busy == 0) begin
                        master_en   = 1;
                        master_data = i/10;
                    end
                    else begin
                        master_en   = 0;
                        master_data = 0;
                    end
                end
                else begin
                    master_en   = 0;
                    master_data = 0;
                end
                
            end
        end

        #200;
        $finish;
    end

    initial begin
        $dumpfile("wave.vcd"); // 指定用作dumpfile的文件
		$dumpvars; // dump all vars
	end

endmodule //testbench